AI Storage Reference Architecture

CPU DRAM is never in this path. The RDMA Write from ConnectX-7 on the stor-node goes directly to the GPU's BAR-mapped HBM3e address space, brokered by BlueField-3 on the GPU node. This is the core latency claim — every other architecture that touches CPU DRAM adds 3–5× latency.

ISA-L EC runs in user space on the primary stor-node CPU — AVX-512 GF multiply completes a 4+2 stripe of a 1 MB blob in ~2 µs. Parity shards dispatched via DPDK over the dedicated replication fabric. ACK returned to writer only after all 3 nodes confirm NVMe write completion.

Content-addressing is the KV cache superpower: if two inference pods computed identical prompt prefix KV blocks, the second pod finds the blob already present (same token hash → same key → cache hit). This eliminates redundant prefill compute and redundant NVMe writes cluster-wide — a capability no filesystem-based system can offer natively.

CXL 2.0 DIMMs on each storage node act as a memory-semantic metadata tier — faster than NVMe by 10–100×, cheaper than DRAM by 3×, and capacity-persistent across reboots. The DHT routing table and hot blob metadata index live here. This eliminates a NVMe lookup hop for every blob access — critical for sub-200 µs end-to-end targets.